Part Number: ADC3669 Tool/software: My project uses ADC3669 for data acquisition, and I am currently debugging the parallel LVDS interface communication between ADC and FPGA to receive ADC data. Like regular debugging, after powering on the FPGA and ADC, first configure the ADC registers to output a fixed pattern such as 0xCC for IODELAY calibration of each Lane（data timing calibration）. Then, configure a new pattern such as 0xF0 for data alignment (BITSLIP), and then put the FPGA into normal real and DDC bypass mode. My question is: When both the ADC and FPGA are not powered off, if the ADC mode is changed( configure the ADC registers ), such as setting 2, 4, or other decimation factors, and the LVDS mode changes to serial LVDS, is it necessary to adjust IODELAY or just re-align the data in this situation?
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