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Forum Post: RE: ADC3664EVM: DCLK and Sampling Clock

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Hi Rob, Thank you for your reply. I got the insertion position for BPF your showed. Is 2dBm(0.796Vpp sinewave) max for DCLIN(650mVpp max)? The VID for CLKP/M for sample clock is 1Vpp(typ) and 3.6Vpp(max). It seems that with 2dBm(0.796Vpp) is not enough level. If my understanding is not correct, could you advice it? I have another question about ADC3644EVM(CMOS interface). My configuration is bypass mode, then ADC3644EVM doen't require external clock for sampling clock and DCLKIN?

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