Hi Daniel, I think all that the ""ninth falling edge of SCL" denotes is marking the start of the next conversion period once data for the current conversion has been read out. In terms of implementing your I2C functions, I don't think it will be too important, unless the clock stretching that happens after is problematic to your controller's logic. I'm a little bit confused by the description in the link you posted to myself. Writing/reading registers and reading data from the device are distinct in that the register read/write has the "write" bit after the 7-bit I2C address, while reading conversion data has the "read" bit after the 7-bit I2C address. I think that would be the reason to why you get conversion data by doing a block read. Lastly, congratulations on welcoming the newest member of your family! Take all the time you need in your response, and we can discuss later. Regards, Joel
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