Part Number: AFE4960 Tool/software: Hi, I am working on integrating the AFE4960 into our design and am encountering issues with SPI communication and EEG configuration. Here are the details of what I have tried so far: Steps Followed: Enable SPI_REG_READ in CONFIG0 Register: As per the datasheet (Section 7.5, SPI Programming), I set the SPI_REG_READ bit in the CONFIG0 register to 1 using the following SPI transaction: txBuf[ 0 ] = regAddress; txBuf[ 1 ] = (data >> 16 ) & 0xFF ; txBuf[ 2 ] = (data >> 8 ) & 0xFF ; txBuf[ 3 ] = data & 0xFF ; HAL_GPIO_WritePin(AFE_CS_GPIO_Port, AFE_CS_Pin, GPIO_PIN_RESET); //CS low HAL_SPI_Transmit(&hspi1, txBuf, 4 , 100 ); //Transmit 4 bytes HAL_GPIO_WritePin(AFE_CS_GPIO_Port, AFE_CS_Pin, GPIO_PIN_SET); // CS high Reading the DESIGN_ID Register ( 0x28h ): I attempted to read the DESIGN_ID register by sending the address and then reading the next 3 bytes using the following methods: Option 1: Full-duplex exchange HAL_GPIO_WritePin(AFE_CS_GPIO_Port, AFE_CS_Pin, GPIO_PIN_RESET); // CS low HAL_SPI_Transmit(&hspi1, txBuf, 4 , 100 ); HAL_SPI_Receive(&hspi1, rxBuf, 4 , 100 ); HAL_GPIO_WritePin(AFE_CS_GPIO_Port, AFE_CS_Pin, GPIO_PIN_SET); // CS high Option 2: Byte-by-byte communication HAL_GPIO_WritePin(AFE_CS_GPIO_Port, AFE_CS_Pin, GPIO_PIN_RESET); // CS low HAL_SPI_Transmit(&hspi1, &txBuf[ 0 ], 1 , 100 ); HAL_SPI_Receive(&hspi1, &rxBuf[ 0 ], 1 , 100 ); HAL_SPI_Receive(&hspi1, &rxBuf[ 1 ], 1 , 100 ); HAL_SPI_Receive(&hspi1, &rxBuf[ 2 ], 1 , 100 ); HAL_GPIO_WritePin(AFE_CS_GPIO_Port, AFE_CS_Pin, GPIO_PIN_SET); // CS high However, I am not receiving valid data in the response. Datasheet Reference: Initialization Sequence The datasheet (Section 8.2.2.1) mentions the following initialization steps: Wait for 1 ms after power-up. Apply a reset (software or hardware). Program all registers except 1Dh (which must be written last). Enable the MCU interrupt service routine only after programming the registers. Write to register 1Dh to set TIMER_ENABLE and RAC_COUNTER_ENABLE bits to 1 , which starts the timing engine and initializes the FIFO. Questions: Register Read Process: Is my approach to reading the DESIGN_ID register correct? If not, what is the proper sequence to read registers from the AFE4960? Configuration for EEG Acquisition: How should I configure the AFE4960 to acquire EEG data (e.g., using internal differencing such as S1-S3 and S2-S3 with bias)? Are there any specific settings or register configurations required for this mode? I am following the Wearable EEG Reference Design from the TI website for hardware implementation. If possible, I would appreciate any specific examples or guidance to help me proceed. Thanks in advance for your help!
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