Forum Post: ADS1220: Issue with Disabling PGA on ADS1220 – Unexpected Gain Values at Higher Settings

Part Number: ADS1220 Tool/software: Hello, I am working with the ADS1220 in an application where it is necessary to disable the PGA because the signal is not at the common mode level. According to section "8.3.2.2 Bypassing the PGA" in the datasheet, when the PGA is disabled, the device uses a buffered switched-capacitor stage to provide gains of 1, 2, and 4, and it states that when the gain is set to greater than 4, the device limits the gain to 4. Test Setup: AVDD and VREFP0 are 3.3V AVSS and are 0V (GND) Reference VREFN0 and VREFP0 are used as VREF I am measuring a differential signal of 0.29 mV which is on a level around 0.9 * VREFP0, which is about 3V above AVSS/VREFN0. Therefore, I need to disable the PGA to remove common mode voltage restrictions. Measurements: At Gain 1 , I get a raw value of about 750. Converting this to voltage gives: 750 / 8388607×3300=0.295 mV At Gain 2 , I get a raw ADC output of about 1500. At Gain 4 , I get around 3000. Because PGA is disabled I expected that increasing the gain beyond 4 should have no effect and I should still receive 3000. However, At Gain 8 , I get approximately 6000. At Gain 16 , I get around 12000. ... I have read register 0 from the ADS1220 again before and after triggering the differential single-shot measurement to verify that the PGA is indeed disabled and remains disabled. In all cases, Bit 0 was set to "1", indicating that the PGA was disabled before conversion and still after. Question: How is it possible that I still get higher values with higher gain settings (>4) even though the PGA is disabled? Am I misunderstanding something? Looking forward to your feedback and assistance! Thank you, Michael