Pedro,
I would like to clarify again that the clock input is a CMOS level input. I do not believe the LVDS drivers that you mentioned above would help the situation. The best way is to use clock drivers with CMOS output to drive the THS5651a.
I also want to clarify the threshold level of the clock input. We specify VIHmin and Vil_max specification for the clock input. At 3.3V DVDD, the VIH_minimum value is 2.1V. This means any input voltage that is *higher* than 2.1V will be recognized as a high logic. VIL_maximum value is rated at 0.9V. This means any input voltage that is *lower* than 0.9V will be recognized as a logic low. This is a fairly standard CMOS level threshold.
The DAC Fclk maximum rating is specified at 70MHz minimum with DVDD of 3.3V. This means the DAC is tested at production all the way up to 70MHz. Therefore, 50MHz input clock will work.
Regarding your testing, please make sure your data input to the DAC matches the two's complement or offset binary code setting. I cannot see the plot that you have uploaded. Please upload the file again. If you have both time domain and frequency domain plot, it will be helpful.
-Kang