Hello Panneer Raja, Both are very good questions that bring up some corrections/additions needed in the datasheet, thank you for bringing this up. For your 1st question, Yes, it is applicable for the 24-bit, DDR, 1-lane, 10MHz sampling rate, the note superscript should appear on the rows where data lines is equal to 1. There seems to be some changes needed on that table. I will submit a change for the datasheet to address this. And for the 2nd question, this has to do with the frame clocking (FCLKP/M), at 10MHz sample clock the minimum FCLK high time is ~50ns and for 20MHz it is ~25ns this is what it ends up being in 2-lane DDR. When in 1-lane DDR that value would technically be divided by 2 and would therefore be below the minimum, so since enabling averaging slows down the FCLK, it is required to be able to reach the minimum FCLK high time needed. Do you have a need for a 1-lane output at 10MHz? Having a 1-lane DDR at 20MHz (with averaging) could provide a similar throughput. Please let me know if there are any more questions regarding the device or anything else I can help with for evaluating the ADS921x devices for your design. Best regards, Yolanda
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