Hi, I believe this is FPGA related issue. Device should not behave like this . Device DCLK will be at 70MHz and you are sampling this in 280MHz ILA clock . Because of this resolution captured data might not be looking correct. 1) Can you check this data at device output on scope to verify the same signature ? This is to verify the device output is coming as expected . 2) Can you change the ILA clock to 560MHz and check this again ?
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