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Forum Post: RE: DAC8162: Is the DAC output held while sending a refresh command?

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Hi Shinichi-san, (a) If you are using the SW reset, depending on the state of DB0, either only the DAC data registers will be affected (when DB0= 0), or all registers will be affected (when DB0= 1). This is what is described in Table 8. If DB0 = 1 during the SW reset command, the power down registers will return to their default which is powered on. DAC data is not retained for either reset mode, so you will need to write new data. (b) The default is all DACs powered up per table 5. If you are going from power up -> power down -> power up, the data registers will be maintained If you are going from power up -> SW reset, the data registers will not be maintained Best, Katlynne Jones

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