Mr Hegde -
I am not sure I understand your question, but I will try to explain a little further.
Table 8 (from the d/s) and your previous post, shows the maximum datarates that are achievable by the ADC. In your case, the fmod frequency is related to the fclk by Table 6...fmod = fclk/40. Then from Table 3...OSR = fmod/fdata = 64. This gives fclk/fdata = 2560 (shown in Table 8 and your above post). For the maximum SCLK = 27MHz, the maximum datarate = 27MHz/2560 = 10547. This agrees with Table 8.
Based on the above, we would anticipate you getting the results shown in the table below
| fclk (MHz) | Datarate (SPS) |
| 1.5 | 586 |
| 3 | 1172 |
| 6 | 2343 |
| 12 | 4687 |
| 24 | 9375 |
Comparing this data, it looks as though you there is a division by 2 difference from your data. Is it possible that you are clocking faster than you think or have a setting that isn't what you think. ie high resolution mode would add an additional division by 2 to the datarates. You may want to check the ADC pins to verify that what you think you are setting is getting to the device. If you are using the EVM, make sure that you aren't conflicting the hardware jumper settings with the port expander settings.