Hi,
The register map looks okay. In ramp mode, all bits should toggle. The LSBs will toggle every clock cycle (in 12-bit, every 4 clock cycles), and each successive bit will toggle at half the rate of the previous bit. Based on the plot it looks like bit 10 is sometimes captured incorrectly and based on the spacing it may occur when bit 11 changes state. My guess is that it's still a timing issue on lane D11_D10.
Not sure what you're asking regarding offset binary mode... In offset binary the most negative value (-1 V differential) is represented as code 0, the most positive value (+1 V differential) is represented as 4095.
Regards,
Matt Guibord