Hi Converter Apps Team,
Once again Thanking you for all your inputs and support you gave us all these days. Please refer to the below link for Schematics,
http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/64/0624.schematic_5F00_audio.png
We are now using PLL for clock generation , setting CODEC in master mode for BCLK and WCLK, and the playback works with good quality. Here is the register dump on recording,
1-AIC3X_RESET 80
2-AIC3X_SAMPLE_RATE_SEL_REG aa
3-AIC3X_PLL_PROGA_REG 91
4-AIC3X_PLL_PROGB_REG 20
5-AIC3X_PLL_PROGC_REG 1e
6-AIC3X_PLL_PROGD_REG 0
7-AIC3X_CODEC_DATAPATH_REG a
8-AIC3X_ASD_INTF_CTRLA c0
9-AIC3X_ASD_INTF_CTRLB 0
10-AIC3X_ASD_INTF_CTRLC 0
11-AIC3X_OVRF_STATUS_AND_PLLR_REG 1
12-AIC3X_CODEC_DFILT_CTRL f5
13-AIC3X_HEADSET_DETECT_CTRL_A 0
14-AIC3X_HEADSET_DETECT_CTRL_B 0
ADC PGA control registers ->
15-LADC_VOL 5a
16-RADC_VOL 5a
MIC Control registers
17-MIC3LR_2_LADC_CTRL ff
18-MIC3LR_2_RADC_CTRL ff
Line1L Input Control Registers->
K19-LINE1L_2_LADC_CTRL 0
20-LINE2L_2_LADC_CTRL 78
21-LINE1R_2_LADC_CTRL 0
22-LINE1R_2_RADC_CTRL 0
23-LINE2R_2_RADC_CTRL 78
24-LINE1L_2_RADC_CTRL 0
25-Mic Bias control MICBIAS_CTRL 0
26-LAGC_CTRL_A 0
27-LAGC_CTRL_B fe
28-LAGC_CTRL_C 0
29-RAGC_CTRL_A 0
30-RAGC_CTRL_B fe
31-RAGC_CTRL_C 0
35-LINE2L_2_LADC_CTRL 78
36-ADC Flag register 0
37-DAC_PWR e0
38-HPRCOM_CFG 10
43-LDAC_VOL 80
44-RDAC_VOL 80
47-DACL1_2_HPLOUT_VOL 98
51-HPLOUT_CTRL d
58-HPLCOM_CTRL 4
64-DACR1_2_HPROUT_VOL 98
65-HPROUT_CTRL d
72-HPRCOM_CTRL 4
82-DACL1_2_LLOPM_VOL 76
86-LLOPM_CTRL 0
92-DACR1_2_RLOPM_VOL 76
93-RLOPM_CTRL 0
94-MODULE_PWR_STATUS 0
95-Output Driver Short Circuit Detection Status Reg 0
96-AIC3X_STICKY_IRQ_FLAGS_REG 0
97-AIC3X_RT_IRQ_FLAGS_REG 0
98-AIC3X_GPIO1_REG0
102-AIC3X_CLKGEN_CTRL_REG 2
107-NEW_ADC_DIGITALPATH 0
Many more thanks,
Dhiv.