Yunjiang,
Regarding your first question, where are you measuring 184.32 MHz? For the TSW1400 firmware, the clock sent back to the FPGA will not match the data clock rate. To measure the data clock rate you will need to measure the clock at the DATACLK pins of the DAC.
The code that you copied a picture of IS NOT from the TSW1400 firmware. The PLL In the TSW1400 FPGA multiplies the FPGA clock to generate the data clock. The example code does not do this, instead it just creates a copy of the FPGA clock. You cannot compare the clocks for the example code to the TSW1400 implementation.
Regards,
Matt Guibord