Suraj, Here are a few quick hints that might help: - Make sure that START and /RESET are both high - The SPI is MODE 1, so that SCLK dwells low and the data is clocked in on the SCLK falling edge - /CS should stay low through the entire communication, not isolated byte-to-byte. For example, if you're writing to the register, /CS goes low, then you send the WREG command, the number of bytes-1, and then the data. After that /CS returns high - Verify that the communications meet the timing and switching specs. As Tom mentioned, get a scope shot or logic analyzer shot to look at the communication lines, and post them back here. It's easiest to help debug communication problems. Joseph Wu
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