I actually think it is sampling interleaving since this ADC has an odd and an even circuit sampler per channel. Datasheet page 59. this thread is similar e2e.ti.com/.../584724 and there are others on the TI forums as well but I am interested in correction for my specific chip. The odd and even samples have a different dc offset and this is causing a spur at fs/2. I can remove it in post processing but it seems that the ADC should have this functionality. The Datasheet hints that it does but also says that the odd and even offset corrections need to be the same so I am confused as to how to implement it.
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