Hi Nikitha, Thanks for your post! 1) Does the ID register read back correctly? 2) Are you following the correct start-up sequence in section 10.1.2 and 11.1? After the power-on reset is complete, /DRDY should begin pulsing at the default data rate (assuming the START pin is pulled up). The /RESET pulse after tPOR is essential for bringing up the digital core in the correct state. 3) Before trying to read the registers, are you sending the SDATAC command? 4) Can you provide a schematic? 5) What is the frequency and how many SCLK pulses are you sending to clock data out?
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