Itabi-san, I believe the reason behind the power-supply sequence comments in the datasheet are due to the AVDD supply being the input to the internal POR comparator. If IOVDD were to come up first, the digital interface would not yet have been initialized by the POR which could lead to device corruption. Similarly the VREF ESD structure on the positive side are connected to AVDD, so if VREF were applied before AVDD the ESD cell would be forward biased and conduct to AVDD, which either has the possibility of damaging the ESD cell or effectively back-powering AVDD which also could corrupt the POR sequence. If all of the supplies come up at the same time then I don't think there should be any problems or risk to damage. I think a good way to validate would be to request an oscilloscope capture of the supplies ramping from the customer. If there is something unexpected happening, we should be able to make some observation from this capture.
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