Part Number: TSW14J56EVM Hello, I am currently using a TSW14J56EVM FPGA mated with an ADC12J4000EVM ADC as part of a radar application. From signal generation to capture there are some slight incoherencies due to the data capture necessarily taking place in the FPGA on the edge of the SYSREF/LMFC. The ADC is sampling at 1.6GSPS in bypass mode with K=4, which should give a SYSREF signal of 10 MHz (from the datasheet - f_sys = 1/t_sys = f_dev/(5*K*F) = 1.6e9/(5*4*8) = 10e6). My question is, is there any way to either obtain this 10 MHz signal as an output somewhere on the FPGA to use for synchronization? Alternatively, can I use the EXT_SYSREF SMA connections on the TSW14J56EVM to clock the SYSREF with an external 10 MHz source? Thank you for your help.
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