Forum Post: RE: ADS8422 ADC nRD timing

Hi,

Thanks for the reply.

I have done a preliminary check to see if I can interface my Compact RIO FPGA system to the ADC and for now I'm using all the interface signals. (I will cut it down later by tying to GND etc when I know that it's working properly)

I think I can get the data to the FPGA, but the timing seems to be much slower than the data sheet spec.

I have attached a logic analyser screenshot. In that, I trigger off the nCONVST falling edge.

There are 2 cursors that I've marked. The 1st one is 'td4' and the second is 'td5'. But as you can see, the times are a lot larger than the specified characteristics. (~70 ns vs ~20 ns)

Do you know why it's so?

Thank you,

Kalhana