Thank you for the reply Greg,
Clock is SCLK, The SCLK was running at 62.5 KHz. After finding equation one, i see that it requires ~5.2 MHz (32kSPS, and 16 bit resolution is default) on the SCLK line. I am using an AT90CAN128 whose max SCLK output is only 2MHz, so how do i use the WREG command when i can't reach the SCLK i need. In the end i do want to be able to write to the Config registers to change the data rate to 1 kSPS and 24 bit resolution, requiring only a ~216KHZ SCLK.
EDIT: Attached is the RREG command (SCLK = 2MHz) for the CONFIG 1. The DRDY goes high when the command is issued, but the datasheet says "... data must be read between two consecutive DRDY signals." i am unsure as to what that means.