Forum Post: RE: Issues in interfacing ADS54RF63EVM and DAC34SH84EVM with Xilinx ML605

Hi Kang,

 Thanks a lot for pointing out the example register files. I am trying to understand what each of those are, with reference to the DAC34SH84 datasheet.

 In order to generate my 270 MHz clock signal, will the loop filter settings in the CDCE62005 also matter? If yes, how should I tune them?

Thanks,
Basil.