Hi Hirotaka,
Vidl and Vidh are the maximum LVDS voltage swing.
First consider the TX_CHA_PDN or TX_CHB_PDN register bits if they can serve the same purpose as the failsafe bias resistors. When these register bits are set, the output of the DAC is forced to mid code.
If you are going to implement failsafe at the LVDS inputs then between 25mV to 50mV pre-bias voltage should be enough.
ADC input pins that are not used can be left un-connected. In your case since you are not using channel B, power down this channel through SPI.
There is no need for the 100ohm differential resistor for the SYNC pin. Just tie SYNCINP to LOW and SYNCINN to HIGH if unused.
Thanks,
Eben.