In ordr for the beep generator to work, you will have to have a BCLK and WCLK. This can be done via an external I2S master or you can configure the AIC to generate the clocks internally.
This requirement is not part of Figure 5-20. This figure just shows the clock tree for the miniDSP, the modulator and the sample rate. You will have to configure this clock tree so that you get the appropriate sampling rate and miniDSP clock.