Hi Calum,
The LVDS standard does not specify the buffer supply voltage. You'll find LVDS devices with supplies from 2.5 V to 3.3 V. The ADS6224 does meet the LVDS standards (1.2-V Vcm, 250 to 450 mV swing). There probably should be a min/max for either the common-mode voltage or the high/low level outputs. However, if you look at an FPGA datasheet, the input common-mode voltage range is typically from less than 0.5 V to greater than 1.8 V. This is a large range that will greatly exceed any PVT variation in the ADC's output common-mode voltage.
Regards,
Matt Guibord