Hi Don,
Thanks for your response, mentioned resource helped me alot configuring the codec's ADC/DAC for 48khz/32khz but my problem is my configuration is not working for 8khz/16khz i am correctly generating MCLK i.e. 2.048MHz for 8khz and 4.096MHz for 16khz, using TLV3204 in slave mode and using MCLK directly as CODEC_CLKIN. AVdd and DVdd is generated internally equal to 1.8V . I am sure my problem is not on the hardware level, there must be some point i am missing while configuring. If you could guide me it would be great help. Thanks.
Regards
zarar