Hi Jonathan,
Welcome to the e2e forum!
Do you have the RESET pin of the ADS8568 tied to a resource on your FPGA? I would suggest that you toggle that pin high after your power on your board. The BUSY output getting stuck may be the result of an incomplete power on reset (POR) due to a glitch on your AVdd rail. If that does not help your situation, please consider posting a schematic of the ADS8568 area on your board along with screen shots of your digital control inputs.