Forum Post: DAC8411 - Timing Requirements for Serial Write Operation

Hello,

I'd like to confirm Timing Requirements for Serial Write Operation.
Test conditions show as followings on the data sheet(on Page7);

<Timing Requirements(correct values)>
In case of AVdd = 3.3V,
1. SCLK cycle = min 50ns
2. SCLK high time = min 25ns
3. SCLK low time = min 25ns

<Question>
If input SCLK pulses(cycle, high time and low time) are shorter as like -Example conditions- than above values , 
does the DAC8411 output false values, or not at all?
If you know, could you tell us?

-Example conditions-
SCLK cycle = 45ns
SCLK high time, low time = 22ns

Then, we promise that we never use under <Example conditions>.
We know this is illegal direction.

Hirorotaka Matsumoto