Forum Post: RE: ADS1281 Timing

Hi AD,

Welcome to the TI E2E Forums!

1. It is not necessary to synchronize SCLK with CLK.
2. The FIR filter takes 62 conversion cycles to settle. At 62.5Hz, this results in a settled conversion after ~1sec.
3. Make sure the external clock period is an integer multiple of the data rate. Otherwise, the conversions may get continuously restarted and you'll never get a settled output.

Pin mode is not used very often with the ADS1281 so I don't have any applications notes on the subject. I think for the most part the timing requirements will be similar to the figure on page 6 of the datasheet (ignoring DIN in pin mode).

One thing I notice from your screenshot is that you are using a continuously running clock. I would suggest just sending SCLKs after a /DRDY pulse to clock out the data, and then stop SCLK until the next /DRDY pulse.

Regards,
Chris