Hey Greg,
Thanks for the response, I hope everything is going well in Dallas.
The EVM suggests using a crystal oscillator (http://www.ctscorp.com/components/Datasheets/008-0256-0.pdf) with the following jitter performance:
Period Jitter, Pk-Pk - - - 50 ps
Period Jitter, RMS - - - 5 ps
Phase Jitter, RMS - - - 1 ps
I assume this would be a sufficiently clean clk source. Is a PLL still necessary? Would there be any significant ADC performance gain from using a PLL? I suppose it could still be useful to make the input frequency a bit more flexible
Is there a good way to predict how the jitter will impact the performance? Will it effect the SNR directly?
Keeping in mind that the ADC performance might be impacted, I assume I can still use the PWM signal shown in the other post to continue working on the formware until I can fix the clock source.
I plan on directly connecting the oscillator to the clock input with just a 50 ohm resistor between. I assume that the 50 ohm resistor suggested by the datasheet and used on the EVM just acts as a LPF to limit the ringing. In the EVM they have two other parts on the output of the xco but they just seem to multiplex between the onboard oscillator and an external clock source.
Also, in the ADS1278 datasheet it suggests that for optimum performance the SCLK needs to be some fraction of the CLK input. How important is this? Do you have an idea of how and why this effects performance? I assume that SCLK and CLK don't need to be synchronized, correct?
I appreciate the help.
Thanks,
Curtis