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Forum Post: RE: DAC8728 latching and power-up sequencing

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Hi Marc,

Sorry for the delay here - I actually went back through the data sheet and realized that the ADS8555 has a slightly different conversion mechanism than what I described last week.  Take a look at page 19, under the CONVST_X description.  The tS3 time is against both the rising and falling SCLK edge because either edge will trigger the start of the actual conversion.  You could sync your CONVSTs with either the rising or falling clock edge and the conversion will start with the next edge.


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