Hello,
I am currently working on interface for ads42lb49 ADC (Xilinx fpga), and I am having problem with understanding SYNCIN pin.
Configuration of adc:
- QDR mode
- 200 MHz clk into ADC (200 MSPS), no internal division
I read in other data sheets, that SYNCIN pin is used to synchronously sample analog data, in case of using multiple adcs.
Q0: If I do not use internal division of clock (inside ADC), is it required to drive this signal, or just connect SYNCINP to GND and SYNCINM to AVDD. If data is always captured at rising edge of CLKINP, do I need to synchronize it? Or in which cases I should synchronize it?
Q1: If I would like to use more than one adc, I assume that, I should drive all of SYNCINP, SYNCINM pins with one signal from FPGA? Or is it unnecessary, because of no ADC internal CLKIN division, and if I imply that CLKIN is synchronous at input pin of every ADC?
Q2: Is it recommended to connect SYNCIN pins? If yes, in which cases?
Q3: Do I need to assert SYNCIN signal after power up?
Q4: If SYNCIN is used, does sync delay register (SYNCIN DELAY, addr 0x7) is meant to be used when I need to compensate path delay?