Forum Post: RE: ADS54J54: Difficulty getting code group synchronization and initial lane assignment.

Hi, I spoke with the person who generated some of the first config files for the EVMs using the LMK04828 with our JESD204b dataconverters, and that section of LMK configuration in lines 111 to 123 were something that he had gotten from some discussion of the LMK configuration, possibly in the clocking forum. At any rate, what that section is doing is first allowing a SYNC event to reset the counters for the SYSREF counter and the clock dividers that are actually being used for the ADC and the FPGA, and then causing a trigger event to reset the counters to synchronize them. Then the sync event is masked and a trigger event issued for the SYSREF itself. it is address x144 that is used first to enable some of the counters to be sync'd. (The comment says enable all outputs to be sync'd but when I look at the value x74 only some are enabled - the ones that are used in our design) Then that same address gets x144 to disable any further synchronizing of the counters. we got this block of code from the LMK people, so I suggest the clocking forum might be better for closer examination of what is going on there. I have not seen an issue with ramp on my checkout of the EVM, Might a see a screenshot of what you are seeing on the most significant byte that doesn't look right? I can't think of anything that would mess up only one byte of the pattern, unless is it the selection of offsetbinary vs two's complement, and that would only result in the most significant bit of the pattern being inverted. Regards, Richard P.