Ran, Set the ADC to all 0, this is the default test condition with HSDC Pro, TSW14J56 and the ADC EVM. Then configure the megacore IP as in the previous post. Keep in mind the SYNC will be inverted. Normally a SYNC low means request for CGS, in this case it is inverted. Just invert this on the FPGA SYNC request out to the ADC EVM. The -1 is always confusing and its something of a difference between software programmers and the standard. K=1-32, means a setting of 0-31 in some cases. Do you have a TSW14J56? Thats always a good place to start as we can try things quickly in the setup to see if they work or not. You can always revert to the working modes if nedded very quickly for a sanity check. Ken.
↧