Hi Ken, Thanks for your support. I will check it first thing. I also tried to change the K to 32. In the ADC gui I can set it maximum to 31 and 32 in the Altera IP. All this issue with -1 is confusing and I'm not sure what need to be. The K=10 should be on the ADC or FPGA? What K value should I set to FPGA and what for ADC? For the Sync~ we used converter at the FPGA. Can we set the Polarity on the ADC GUI? Thanks, Ran
↧