Hi Harm Lok,
Sorry for the delay. I was researching the design documentation.
IN principle I don't see anything wrong that you are doing. To enter the High Speed mode (Hs) you ned to send out the master code. After the master code byte the Master switches to Hs, and all following transactions will be in Hs. Until the STOP symbol is issued.
Now, my question to you is: what makes your MASTER slow down the bus?
The DAC121C021 has no means of slowing down the SCL rate: this device does not support clock stretching, as a matter of fact SCL pin of the ADC is input only.
All that happens on the ADC when the master code is issued, is the enabling of the SLEW RATE control on the SDA output buffer. If you tried to run the bus at 3.4Mbps without sending the MASTER code first, the ADC would not care, it would try to keep up , and probably generate a bunch of data errors, but it would not slow down the bus.
Is it possible that your MASTER drops the data rate on its own?
Just a thought.
Sincerely,
tom