Hi Primoz,
The conversion will start as soon as the digital filter is reset and this takes place as soon as the MUX0 register has been written (relative to the falling edge of the last SCLK of the WREG command). The timing for the conversion to complete will be based on a specific number of clock cycles shown in Table 12 of the datasheet. The actual time will depend on the clock frequency. When using the internal oscillator, the time can vary +/- 5% of the time shown in Table 12. To be safest, you should add another 5% to the time (105ms) or slightly longer when using the timer method. Use of an interrupt driven system for DRDY is the best method for ensuring valid data, followed by DRDY polling and then timed methods.
Best regards,
Bob B