Hi Ryuji
You are correct, the test pattern goes in sequence D15, D14, D13, D12, ..., D2, D1, D0, D15, D14,... continuously repeating until it is disabled.
If the ADC test pattern is enabled and active when the ADC SYNC is asserted and de-asserted, the test pattern will be running as soon as the ADC finishes the synchronization pattern. However there is no guarantee that the D15 value of the test pattern will be the first group of data output after the synchronization pattern finishes. The first value of the data frame could be at some point in the middle of the ADC test pattern sequence.
In addition, whenever the ADC test pattern is started, there is no guaranteed relationship between the start of the pattern and the output data frame. This is due to the asynchronous nature of the ADC test pattern enabling.
I hope this is helpful.
Best regards,
Jim B