Greg,
After making stronger signal driving capability for SCLK, MOSI and CS\, I captured the following picture.
Ch3 is SCLK with 5MHz; Ch2 is DRDY, Ch1 is MOSI with 0xAA data, Ch4 is CS\ signal.
I verified the following timing requirements for the Fig1 in the page 8: tCSSC, tSCLK, tSPWH, tSPWL, tDIST, tDIHD, tCSH, tSCCS, tSDECODE
For now, I have no concern about the timing requirements for MISO since it is not related to ADC initial setting.
So overall it seems good in timing wise. But I am still not able to set fDR other than 32kSPS.
Ming
