Satoshi-san,
I have modified the DAC5688 configuration file to fit the DAC5688 PLL mode. The changes are:
1. changed the input clock configuration per page 33, table 5, PLL mode with CLKO. The assumption for this is based on your DAC5689 setting.
2. Changed the PLL gain and PLL_range configuration in config0x1E based on the table described on page 8 of datasheet. The customer may use other range if needed, but this is the test range at the production.
-Kang