When I set the SCLK in ADCPro to 66.66MHz it changes it to 67MHz and the maximum data rate is 966.086lHz. This then reduces the clock to the ADC to 67MHz but also reduces the sample rate to 966.086MHz.
In order to run the ADC at the full specified rate the ADS8881EVM used a 80MHz clock for SCLK to the ADC.