Hi Ryuji
Regarding your latest questions:
1) Correct. The training pattern will completely finish and then the outputs will transition to ADC data.
2) When SYNC is asserted, the data outputs will transition to the training sequence tLAT_SYNC Fclk cycles later. This will happen regardless of what portion of the test pattern is being output.
3) Sync/Delay Enable must be set to 1 to enable the output test pattern. Therefore it is recommended to set it to always 1. If can be set to 0 to reduce power consumption, but will need to be set to 1 before re-synchronizing the serial data link using the SYNC input. The power reduction is a small percentage of the overall device power consumption, so it may be easiest to simply leave this bit set to 1.
4) The power-on calibration delay of the LM97600 is fixed. The delay period is 8,388,608 Fclk cycles. This will result in an approximate delay of 3.35 ms for a 2.5 GHz input clock if the clock is active and stable as soon as the LM97600 power is applied. If Fclk is turned on after the LM97600 power is applied the delay will be less predictable since the input clock receiver can toggle on noise prior to the activation of the Fclk source. A manual on-command calibration should be performed once the LM97600 has been configured into the desired operating mode (number of inputs, selected inputs, etc.) and has stabilized close to the final device operating temperature.
I hope this is helpful.
Best regards,
Jim B