Forum Post: RE: DAC5681Z - CLKIN status during SIF registers programing

Hi Benjamin,

You do not need to guarantee timing between CLKIN and DCLK because an internal FIFO will absorb any skew. However, they both need to come from the same time base.

I would expect this to be fine. What clock source are you using? Most high quality clock sources are better than +/- 10% duty cycle.

Regards,
Matt Guibord