No success,… Some time ago, I have tried your reference config files from the GUI but I always had the same problem with the interleaving correction. So I don’t think that the problem is related to the config files. I also don’t think that there is something wrong with the ADC or the eval board,… I also bypassed the LMK VCO (LMk in clk distribution mode) and have used my own clk without success,.. Is it possible that the JESD interface (Xilinx FMC interface or the IP) influences the IL correction in some way? What else could have influence on your IL correction? I have also tested your TSW38J84 on the VC707 witch works great under every condition,… Best regards! Martin
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