I'm currently writing some FPGA code to de-interleave the 4-channel D1 TVP5158 output and have a few questions:
(1) The 4-ch pixel-interleaved mode timing diagram on page 23 of the TVP5158 datasheet starts with an SAV code (FF 00 00 xy) for CH1, and appears to indicate that CH2 comes out four time-slices earlier, and CH 3 comes out two time-slices prior to CH2 , and CH 4 comes out four time slices prior to CH3 (a time-slice being a four-bit grouping of interleaved pixels). Is my understanding of this correct, or does it vary, depending on when the output formatter can put them together?
(2) Not shown on the timing diagram is the start of the other three channels. Are the FF 00 00 xy EAV/SAV codes present on all four channels, or just on CH1?
(3) It is my understanding from other posts on this forum that the active video time between the SAV code and the EAV code is constant per BT.656, but the blanking interval may vary, depending on the whim of the output formatter. Is this correct? The datasheet says "Each channel video data is compatible with ITU-R BT.656 format", which would lead me to believe the blanking intervals should be constant and standard, but apparently this is not the case.
(4) Is the 108MHz clock constant, or does it vary as well, based on the output formatter?
My goal is to find some formatting aspect of the interleaved datastream which will allow me correctly de-interleave the four channels, so I need to find some timing marker (such as one of the FF codes, or an EAV sequence) to reset a 2-bit pixel counter that will tell me which channel a pixel is on, as well as generate a reset for a divider to generate a constant 27MHz output clock from the incoming 108MHz clock.
Thanks!