Hi Reed,
For the ADS8528, the expectation is that there will be 32 clocks, with the first four output bits being 'zero' followed by the 12-bit conversion result of CHx0. From there, the device will output another for zeros followed by the conversion results of CHx1. The leading MSB should always be zero and I suspect what you see is a remnant of the LSB getting shifted out on the first SCLK with a 31 clock cycle transfer. Add the 32nd SCLK and see if that clears up the problem.