Hi,
i sent the source code for the parallel data format (as that is the code for the part number you called out) to the address provided. You would need to do some editing to port over the ADC interface portion of the code, but i also sent a sketch of how i use the IDELAY and IDDR cells to meet timing into the FPGA. You would need to determine what your IDELAY tap settings would need to be to meet timing,and you would need to edit the constraint file to match the pinout you will end up with into your FPGA. Much of the code is the buffer memory and a simple UART port to move the captured data out of the FPGA. You would need to put your code for that in place of what you find there.
Regards,
Richard P.