I'm using the ADS131E04 to digitize the outputs of a triaxial accelerometer array. The ADC is set up as follows:
1. f_CLK is 2.048 MHz.
2. f_DR is 2 KHz. This gives an f_DR / f_MOD ratio of 0.002.
Each sensor's signal BW is 1 KHz.
I have a 2nd order LPF between each sensor's output and its ADC input channel. Referring to the attached PDF, my inclination is to design the LPF so the input signal amplitude will be no greater than the ADC's resolution limit at f_MOD / 2, to avoid aliasing. But, this choice compromises the signal BW a bit.
My question is: Does the above decimation ratio give enough rejection of any frequencies over f_MOD / 2 so I can move the LPF poles out to preserve the sensor's signal BW?