MIN of High-level input voltage for SPI lines is 1.3V and MAX of Low-level input voltage is 0.4V. So, 1.8V of CMOS should be fine with up to 20MHz of SCLK. tSLOADH (SCLK to SEN hold time)is MIN 25ns shown from Table 9 in datasheet. Have you triggered RESET before SPI configuration?
Thanks,
KW