Hi Hans, Section "8.5.2 Data Format" of the data sheet shows how to convert between ADC code and voltage. The voltage value would essentially be the ADC code in decimal * voltage value of 1 LSB. Best Regards, Angel
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Forum Post: RE: ADS1220: Only returning 0xFFFFFFFFFF after sending RDATA command
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Forum Post: RE: ADC12QJ1600: Connect a JESD lane from another ADC to the same GTH Quad
Hello Hiromu, Yes the easiest thing to do is to route all clocks from a single clocking chip. Such as the LMK04828. There are not any good documents and it will depend on the sampling frequency the customer wants to use as well as the JMODE of the ADC they pick. Additionally if they are looking into using a single clocking chip for all the ADCs it might be easier for them to generate the sampling clock external oppose to the internal PLL, but this is something they would have to evaluate. Thanks, Eric
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Forum Post: RE: ADC3660: Changing DCLKIN changes measurements
Hello, You are correct that these registers are not written to in the configuration I provided above. This is because the DCLKIN Buffer is enabled by default, meaning 0x18, bit 4 and 0x1F bit 6 are set to 1 by default. In 1W, Real Decimation mode, the output data is serialized, and the DCLKIN Buffer must be enabled. If you have any other details about your application that is relevant to the config, let me know and I can help you get a working config. If needed, let me know and we can move this discussion to an email. Best, Luke Allen
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Forum Post: RE: ADS127L11: Voltage reference changes are ignored when using the THS4551 FDA
Hello David, The code noise will go up as the reference voltage is decreased. The input voltage noise remains the same, but the change in codes will go up. For example, if you have 100uVpp of noise and each code change represents 1uV, then you will see 100 code changes. If you now reduce the reference voltage by 1/2, each code now represents 5uV, so the codes will change by 200 for the same 100uVpp of input noise. The FDA has a relatively low input impedance. For example, if you are using a feedback value of 1000ohm, and an input value of 100ohm to get a gain of 10, Rf/Rg, any source resistance from your input connections will reduce the overall gain. In this example, a source resistance of 10ohm will result in an overall gain of 9, 1000/(100+10)=9.09. O.K., understood you are accounting for repetitive data, in which case, you can ignore the DRDY. If you are reading data at a faster rate than the output data rate (default is 400ksps), then you will occasionally get repeated readings, but you should always get the correct input value after additional readings. The above scope image shows the input value near zero, slightly negative. If you are using a 4.096V reference value, and standard input range with 1x (all default values after power-up reset), then the input voltage level for the above scope capture is about -22.95uV. In order to debug this, using your scope, capture the SCLK/SDO with a non-zero DC input level and 4.096V Vref, then repeat with Vref equal to 2.048V. If we see the approximately correct output code from the ADC, then you know there is something wrong in your code that converts the data. Also, since you are using a reference voltage of 4.096V maximum, you need to set the REF_RNG bit in the CONFIG1 register to 1. The ADS127L11 defaults to the low range on power-up. Regards, Keith
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Forum Post: RE: ADS1261: Responding with All Zeros Part 2
Bryan, I thought we had the CS tied correctly to the chip select output of the Xilinx SPI bus so that when I write the slave select to the Xilinx SPI configuration register and it selects the slave it raises the CS on the correct slave. But obviously this is not the case since apparently the CS line is not moving. I will check all previous plots to see if CS was at one point moving. Maybe I changed something in the Xilinx SPI bus configuration registers which broke it and it is no longer driving CS. Or maybe as you say, it is indeed tied low, I will check with HW. I agree with you that failing to drive CS correctly may be the cause of the problem. I am curious why some commands work consistently for multiple commands in a row and some do not work at all. But perhaps that is a distraction to solving the problem if CS is the root cause. We are re-spinning the board soon and in the next revision I will be given directly control over the CS line. I've tried everything I can think of in the software at this point. So let's close this issue for now! I don't think it will be beneficial to spend any more time on it until CS is driven correctly. Hopefully that will solve the issue. If not then we will have to choose a different TI-ADC since we can't change the processor SOC. Many thanks for your help and quick responses.
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Forum Post: RE: ADS1261: Responding with All Zeros Part 2
HI Everett Everett, I would also recommend getting an EVM. This will establish an operational baseline that you can benchmark against what your controller is doing. You can also verify your HW with our controller / GUI (by fly wiring them together) to make sure there are no HW issues either (so far we have assumed this is purely a software / communication issue) The ADS1261 is more than capable of operating using a standard SPI interface, as are most of our other precision ADCs. But they all communicate roughly the same way, so it is possible that if this is a comms issue, choosing a new ADC will not resolve it. -Bryan
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Forum Post: RE: ADS114S08EVM: The voltage across C88 is higher than the voltage at the ADS114S08EVM input terminals A8 and A9.
Hi Shinichi Inoue, I am having some issues with my setup, but I will try this again tomorrow Can the customer try the same experiment using a 1.5V battery between AIN8 and AIN9 instead of the DC source? They will need to reduce the gain to 1 (or maybe 2), but I would like to see if they still get the "spikes" when the entire system is floating Also, is the customer using our GUI to collect data, or their own software? -Bryan
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Forum Post: RE: DAC38J84: DC performance
Hello, Marijn, I have asked one of the apps engineer Matt Kramer, to look into this for you. He will respond in a day or two on the recommendations. -Kang
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Forum Post: RE: ADC121S021: ADC121S021 with Op-Amp
Hi, I appreciate your response. Please check the attached schematic for your review. i) Using ADS8665 to directly interface the sensor with the microcontroller. ii) Using ADC121S021 with an op-amp circuit. Kindly review and confirm the connections. Please let me know if any improvements are needed to ensure accurate output. I would greatly appreciate it if you could also provide some PSpice simulations for better understanding for op-amp circuit. Thank you!
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Forum Post: RE: ADS131B04-Q1: Offset difference between power modes
Hi Dries, LDO is always recommended for ADC, switching power supply will definitely introduce additional offset error, however the layout or other design probably caused this error in your test because you could see a small error when using internal short. I do not think adding or changing series resistor value will help to reduce the error because our EVM also uses 1kohm series resistors and 1kohm value is not too high to introduce significant noise or have an impact on the offset error measurement. I'm not sure if you tried a test before, remove the series resistors on both AINP and AINN pins and disconnect the input from the shunt, just short both pins together as close as to the input (probably on the position of 100nF differential capacitor) and tie them to analog ground. BR, Dale
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Forum Post: RE: ADS7028: Maximum input frequency
Can you provide guideline for designing the ADC driver circuit and other front end components to support 50kHz signal?
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Forum Post: ADC08B200: ADC with >3KByet capture buffer
Part Number: ADC08B200 Tool/software: Hi, I am looking for a 150-250 MSPS ADC (preferably dual channel) with a buffer size of > 3KBtye? (basically looking for a part similar to ADC08B200 with larger buffer size). Would you be able to propose a part? Thanks × Selected text must contain at least 2 dots (be more than 2 levels deep)
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Forum Post: RE: DAC8565EVM: DAC CONNECTON ISSUE
Hi Amara, Each DAC channel has a temporary (buffer) register and an active register. The command you were doing before was to load the temporary (buffer) register data into the active register which will update the output. If code 0 is in the temporary register (the default) then you are just moving 0 to the active registers which will just set the outputs to 0V. This command matrix should help you understand which codes to write: 0x348000 triggers the highlighed command: If you want to use 0x30000 to update all outputs with the data from their temporary registers: You need to write to each of the temporary registers first with DB18 and DB17 selecting which channel is being written to: You can also write to each channel's temporary register and update the output for just that channel at the same time with: Maximum reference is determined by this condition: AVDD – (VREFH + VREFL) /2 > 1.2V. Technically the max voltage is AVDD is VREFL is AVDD/2. Best, Katlynne Jones
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Forum Post: RE: ADS7138-Q1: Abnormal read register value, unable to successfully write register
Hi Joel Meraz, Summarize the current situation: Currently, the operation of reading I2C registers is verified to be able to successfully read the value of a single register. I read many registers with default values other than 0x00 according to the chip manual, and the results were all correct. In addition, the operation of writing I2C registers and verifying can also successfully change the value of a single register. Just as writing the value 0x02 to the 0x01 register, the verification code before and after writing is valid and successful. Taking the 0x01 register as an example, the data captured by the logic analyzer for reading/writing registers currently conforms to the format specified in the chip specification. Read 0x01 register Write 0x20 to the 0x01 register Read 0x01 register again However, when pressing the physical button, reading 0xA0 will still be 0x00. I also read all the registers related to CH0 once. The results read when pressing the physical button do not look like AD values. So I would like to inquire: 1. Are there any registers that need to be configured to enable the AD chip to process and convert analog signal inputs? 2. Which register is being read to read the AD value of AIN0 input? Is it Recent_C0_LSB and Recent_C1_LSB or other registers? Regards, Ziming Yi
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Forum Post: RE: TXB0108: TXB0108 - Open drain pin support
Hi Jack, We are implemented the design based on the TXB for open drain. From the funcionality wise, we are not facing any issue. Will it create any issue for TXB IC. Without external Pullup, the line is not going to high. That's why we have added external pullup. Thanks, Jeeveth K
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Forum Post: RE: AFE5851: LOW_FREQUENCY_NOISE_SUPPRESSION and VGA gain.
Hi, It is explained in datasheet .
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Forum Post: RE: AFE5851: LOW_FREQUENCY_NOISE_SUPPRESSION and VGA gain.
You may think so, but 2 persens here read it in different ways, this is why I ask for how it works instead of what effect it has. Also, can you explain why the gain is as it is? BR Torleif.
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Forum Post: RE: AMC1303E2510: About Chopper Frequency
Hi,Alexander-san, Thank you for your reply. I'm a FAE at Dinsty, the same team as Toshi-san. I understand that even if the internal CLK is 10MHz or 20MHz, the chopper frequency is fixed at 625kHz, not fclk/32, and is the same. Has the chopper frequency been fixed at 625kHz since the AMC1303 was first released, even in models with an internal Clk of 10MHz or 20MHz? Thank you and best regards Hiroaki Yuyama
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Forum Post: ADS127L18EVM-PDK: TDM mode configuration
Part Number: ADS127L18EVM-PDK Other Parts Discussed in Thread: ADS127L18 Tool/software: This is related to the same evaluation than in question https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1478299/ads127l18evm-pdk-an-issue-in-ads127l18-configuration-via-spi/5676049#5676049 Single channel works nicely with all tested sample rates 32Ksps - 512Ksps, but we have not been able to find a way to configure ADS127L18 to use two channels in time multiplexed mode with 64Ksps i.e. using only D0 data lane. Expectation was to get samples from channel 0 and 1so that when there is no signal in channel 0, every second sample value is near zero and status byte carrying channel numbers 0,1,0,1... Configuration below, can you find an error in it? ----- retVal |= ratSpiWriteAds127Reg(GEN_CFG1, 0); // default retVal |= ratSpiWriteAds127Reg(GEN_CFG2, 0b00000110); // fclk 32.768Hz instead of internal 25.6MHz retVal |= ratSpiWriteAds127Reg(GEN_CFG3, 0b10000000); // full output slew rate in SAI, comment out for default slower one // DP_CFG1 Texas suggested 0b01110000, difference in bits 5-4, which would mean 8 data lanes retVal |= ratSpiWriteAds127Reg(DP_CFG1, 0b01000000); // data port status byte enabled, one data lane // DP_CFG2 is mode depending // CLK_CFG is mode depending // GPIO registers are at default values (low disabled outputs) // CHn_CFG1 default values (normal polarity, normal range, buffers disabled) // CH0_CFG2 and CHN1_CFG2 is mode depending retVal |= ratSpiWriteAds127Reg(CH2_CFG2, 0b00100000); // power down retVal |= ratSpiWriteAds127Reg(CH3_CFG2, 0b00100000); // power down retVal |= ratSpiWriteAds127Reg(CH4_CFG2, 0b00100000); // power down retVal |= ratSpiWriteAds127Reg(CH5_CFG2, 0b00100000); // power down retVal |= ratSpiWriteAds127Reg(CH6_CFG2, 0b00100000); // power down retVal |= ratSpiWriteAds127Reg(CH7_CFG2, 0b00100000); // power down // CHn offsets and gains at default values 0 offset 1.0 gain switch(sampleRate) { case 512: // 512Ksps, one channel retVal |= ratSpiWriteAds127Reg(DP_CFG2, 0b00000000); // DCLK is 32.768 retVal |= ratSpiWriteAds127Reg(CLK_CFG, 0b00001000); // ext clock, div by 1 retVal |= ratSpiWriteAds127Reg(CH0_CFG2, 0b00000000); // OSR32 retVal |= ratSpiWriteAds127Reg(CH1_CFG2, 0b00100000); // power down, using only CHN0 break; case 64:// 64Kbps, two channels retVal |= ratSpiWriteAds127Reg(DP_CFG2, 0b00000000); // DCLK is 32.768 retVal |= ratSpiWriteAds127Reg(CLK_CFG, 0b00001011); // ext clock, div by 4 retVal |= ratSpiWriteAds127Reg(CH0_CFG2, 0b00000001); // OSR64 retVal |= ratSpiWriteAds127Reg(CH1_CFG2, 0b00000001); // OSR64 break;
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Forum Post: RE: TSC2004: Touch Screen not responding properly.
Thank you for the suggestion. We'll give it a try and update you on the progress.
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