Thank you for the engineer's reply! However, according to the datasheet, SRB2 is indeed set to "0: open". Therefore, I entered 0x05 in CHnSET. This setting should correspond to SRB2, right? My current configuration has nothing to do with the comment!
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Forum Post: RE: ADS1299：Incorrect Test Signal
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Forum Post: TX7316EVM: TX7316EVM
Part Number: TX7316EVM Tool/software: Hello, I have recently purchased a TX7316EVM. I am using it 5 level mode. I am trying to generate a 10MHz 4 pulses signal. I tried many options in "Profile configaration" but is not able to generate a 10MHz signal. Can you help me with this? --Surojit
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Forum Post: RE: ADS1278EVM-PDK: ADS1278EVM-PDK
Thank you for the fast reply. When configuring everything as described: S3 right (onboard ref), S6 up (SPI mode), S2 everything down (ground) except CLKDIV is up (VDD), JP1 and JP2 open and all the power pins connected via jumper cables to MMB0, the SCLK pin already provides a clock signal with a 27MHz frequency. I'm not sure I understand what you mean with activate SCLK as it seems activated upon powerup in this setup. I'm guessing you meant pulling the SCLK signal to low from outside to keep it in 'idle mode' as you describe it, but I am not sure about that since the CLK pin is connected to SCLK so both would be low? The DREADY signal stays always high in this setup. Also nothing except a scope is connected to the output pins of the eval board in my setup. Regards, Nik Krevelj
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Forum Post: RE: ADS1299：Incorrect Test Signal
Solved Thanks
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Forum Post: ADS131M02: Read voltage
Part Number: ADS131M02 Tool/software: Hi Team, All I do is attempt to read voltage.Potentiometer is what I use to provide voltage. Kindly lead the way for me. Methods of Reading Thanks & Regards, Pavan
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Forum Post: RE: ADS1220: returns full scale data in Two-wire RTD
e2e.ti.com/.../adc_5F00_troubleshoot.zip I've attached a zip with images of the requested captures. It contains attempts with both single-shot and continuous mode and the images are numbered in order in which they happened. We are issuing START/SYNC when using single-shot mode after setting the registers. This is followed by a 1 second delay, after which we read the 3 bytes. In continuous mode we are reading 3 bytes with RDATA command every second after setting the configurations. So currently we are only using delays to make sure the conversion result is ready when we read the bytes. In every case the 3 bytes read are 7F FF FF.
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Forum Post: RE: ADC3643: Timing
Hi, You are correct that the data leads the clk and hence the negative number Regards, Geoff
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Forum Post: RE: ADC32RF55: Initial Device Configuration After Power-Up
Hi Shunya, Yes, 0x7B refers to channel AIN1/2 while 0x8B is for inputs BIN1/2. I am going to close this post and send you an email so we can have this discussion over email. Please be on the lookout and check spam folders. Thanks, Chase
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Forum Post: ADS1282: FSC and OSC value at start of calibration
Part Number: ADS1282 Tool/software: Hello, I am using the ADS1282 and need a calibration sequence. I already asked questions about the sequence in the past (does offset calibration need to be before gain calibration, etc). I realise now I forgot 2 questions, but the previous thread is locked. 1) Do we need to reset the OFC and FSC value to their initial value (0 and 1.0) before starting the sequence, or do the OFSCAL and GANCAL command automatically uses the initial values to avoid compounding gains/offsets? For example, if the gain is manually configured at 0.5 before GANCAL and I apply a FSR input value (+2.5V with PGA = 1), what will the calculated gain be? I expect it to either be 1.0 if the OFC/FSC registers are ignored during calibration, or 2.0 if they are not ignored during calibration (so that 0.5 * 2.0 = 1.0). But if the calculated gain of 2.0 is applied, it will produce erroneous results, because it is only valid in conjunction with the 0.5 gain used at the start of calibration (overwritten to 2.0 after the GANCAL command). 2) What happens if the calibration parameter generates a value outside of the allowed range? For example, if I have a +2.5V with PGA=1 input, it is within range throughout the processing chain. But if FSC is set for a gain of 2.0, it will become out of range in the calibration block. - From the block diagram, is it right to say that the MFLAG would not be asserted? - Would the redundant LSB flag the issue? - If the answer to point 1 is that FSC/OFC are NOT ignored during calibration, what would happen in this case? The input range is respected, but the scaling causes issues by exceeding output encoding width. Does this encoding width issue affect the calibration logic? Thank you for your support, Vincent
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Forum Post: RE: DAC5687-EP: DAC5687 SPI Communication Error
Hi Chase, I was out of office last week. I will send the schematics in a few days. Best Regards, Mustafa
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Forum Post: RE: ADS7138: Use Satellite project
Hi Kimura-san, Using commercial-grade devices for space is not recommended, as they are not designed or validated to handle radiation exposure. Using the part in such applications is not restricted by TI, but we recommend against this activity. If you decide to use this device, we encourage you to test the device accordingly to ensure proper functionality and longevity. TI will not guarantee the functionality and longevity of the devices as they are being operated beyond its design capabilities. We offer the ADS128S102-SEP , a cost-effective space device for low to medium earth orbit. This device can pass 30KRAD TID and 43MeV SEE, and TI guarantees proper functionality and longevity during radiation exposure. -Kyle
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Forum Post: RE: DAC11001B: DAC11001B 0-5v
Hi, Post a clearer a schematic, not able to read net names and part numbers. Regards, AK
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Forum Post: ADS1299: Regarding the deviation issue between internal signal testing and external signal testing.
Part Number: ADS1299 Tool/software: Firstly, when testing the internal square wave, the values of the square wave signal were+1.36mV and -2.37mV, respectively, instead of the standard+1.875 and -1.875mV. Set the MUXn [2:0] of CHnSET to 001 for internal noise short-circuit testing, and the measured noise value is -0.5mV. Then, when testing the external signal, I grounded the p-terminal and n-terminal of the channel, and the measured value was around -0.47mv. May I ask what caused this? How should I solve this problem. I would be extremely grateful if a solution could be provided.
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Forum Post: RE: TLV2553: TLV2553IDWG4 : Life Cycle status
I want to know if the specific part TLV2553IDWG4 is active or discontinued.
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Forum Post: RE: ADS1278EVM-PDK: ADS1278EVM-PDK
Thank you for your help! The problem was that the SCLK pin wasn't connected directly to ground but was floating, that meant it wasn't really low, so the DRDY pin couldn't work. I also made a mistake when creating notes from the datasheet and accidentally switched test points for CLK and SCLK (TP6 and TP8) - they were actually working correctly meaning CLK was 27MHz and SCLK wasn't driven and was floating. Now that I connected SCLK to ground the DRDY pin is low and goes high at 105ksps. Now I can connect the board to the external MCU and start testing my code for SPI communication. Thank you very much again for the fast and very helpful replies! Best regards, Nik Krevelj
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Forum Post: RE: DDC264EVM: Difference between channel A and B
Hello Jonathan, 1. The DDC264 contains 64 identical input channels that perform the function of current-to-voltage integration followed by a multiplexed A/D conversion. Each input has two integrators so that the current-to-voltage integration can be continuous in time. The DDC264 continuously integrates the input signal by switching integrations between side A and side B. 2. Yes that is correct. Average code is the average of the 512 samples / codes. 3. Yes, each nDVALID corresponds to a side A or side B. Hence the value in nDVALID Read is split between A and B sides. Yes, the 512 values / samples are arranged as time series data and yes, the integration time is same across samples.
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Forum Post: RE: AFE5818: AFE5818 register configurations
Are there any tools available for configuring ADC registers to generate a coefficient file?
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Forum Post: ADS1000-Q1: Input impedance dependency over temperature
Part Number: ADS1000-Q1 Tool/software: Hello, My customer is investigating ADS1000-Q1 and they're wondering the input impedance dependency over temperature. Is it possible to show the data for non NDA customers just as a reference? Best Regards, Yoshikazu Kawasaki
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Forum Post: RE: AFE58JD32: Max sampling frequency for JESD 2 lane config
In 2 lane mode 8 channel will come on each lane .So below is the calculation of lane rate; 8(No adc)* 12 (Serialization factors) * 10/8 (jesd 8 bit to 10 bit encoding) * Fs(sampling freq) With 40MSPS we can see lane rate is 4.8GBPS. The device supports 5GBPS lane rate and that will correspond to 41.66MHz sampling frequency. But for a shorter trace length we can push the speed till 6 GBPS. Datasheet has this information. In that case we can go till 50MHz.
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Forum Post: ADS1293: GAIN issue and design question - Analog and Digital Filtration - 2 LEAD Holter to pass IEC 60601-2-47
Part Number: ADS1293 Tool/software: Hej! I'm having GAIN accuracy issues on a ADS1293 device where I see a offset of about 15-17% from a input signal on the ADS output. We have a battery powered Holter device for logging ECG data through a 2 LEAD, 3 electrodes configuration, (IN1 = RA, IN2 = LA, IN3 = LL). We use two channels configuered as: INA_CH1 = LA-RA INA_CH2 = LL-RA. The CMDET is enabled and takes the three IN and routes them through CMOUT to RLDINV through a 10kOhm resistor and to RLDOUT through a 1MOhm resistor. The RLDOUT is routed on the PCB to the three leads with three separete 10MOhm resistors and 150pF caps. We have a 1st order high-pass butterworth filter in sw which I can enable/disable and edit if possible. The PCB design is pretty much set, we could change some values if necessary. We need to pass IEC 60601-2-47 where the pass criteria for GAIN accuracy is 10%. To the question: When I send in a known input signal to the ADS from our signal generator, I get about 15-17% offset on the measuered output compared to the input, both with the digital filter enabled and disabled. The input is a 100ms impulse with amplitude of 2mV-10mV. What could cause this constant gain change?
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